1. Field of the Invention
The present invention relates to a structure of a nonvolatile semiconductor memory device, and more particularly to a structure of a flash memory using an SOI (Silicon On Insulator) substrate. The present invention also relates to a semiconductor integrated circuit such as an LSI in which the nonvolatile semiconductor memory device is formed.
2. Description of the Background Art
FIG. 46 is a cross section schematically showing a structure of a memory cell transistor in a flash memory using a bulk substrate (which refers to an ordinary semiconductor substrate, not an SOI substrate). In an upper surface of a silicon substrate 101, a source region 102s and a drain region 102d which are paired are formed away from each other. On the upper surface of the silicon substrate 101 in a portion between the source region 102s and the drain region 102d formed is a multilayer structure in which a gate oxide film 103, a floating gate 104, an insulating film 105 and a control gate 106 are layered in this order. On a side surface of the multilayer structure, a sidewall 107 is formed of the insulating film.
In a write operation of data, a high voltage is applied to the drain region 102d and the control gate 106 with a g round potential applied to the source region 102s, for example. Through this application, hot electrons generated in a high-field region near a channel region and the drain region 102d are implanted into the floating gate 104.
FIG. 47 is a cross section schematically showing a structure of a memory cell transistor in a flash memory using the SOI substrate. An SOI substrate 108 has a multilayer structure in which a silicon substrate 109, a BOX (Buried Oxide) layer 110 and a silicon layer 111 are layered in this order. In the silicon layer 111, a full-isolation insulating film 112 extending from an upper surface of the silicon layer 111 to reach an upper surface of the BOX layer 110 is selectively formed. In an element formation region defined by the isolation insulating film 112, the paired source region 102s and drain region 102d are formed away from each other. A bottom surface of the source region 102s and that of the drain region 102d reach the upper surface of the BOX layer 110.
Further, on the upper surface of a body region, that is, the silicon layer 111 in a portion between the source region 102s and the drain region 102d formed is the multilayer structure in which the gate oxide film 103, the floating gate 104, the insulating film 105 and the control gate 106 are layered in this order. On the side surface of the multilayer structure, the sidewall 107 is formed of the insulating film.
FIG. 48 is a circuit diagram showing part of a configuration of a memory cell array in the flash memory. FIG. 48 shows a configuration consisting of only fifteen memory cells in a matrix with five rows and three columns. Each memory cell comprises the memory cell transistor shown in FIG. 47. The control gates CG of the memory cell transistors in the memory cells belonging to a row are connected to a common word line. For example, the control gates CG of the memory cell transistors in the memory cells MC11 to MC13 are connected in common to a word line WL101.
Further, sources S of the memory cell transistors in the memory cells belonging to a row are connected to a common source line. For example, the sources S of the memory cell transistors in the memory cells MC11 to MC13 are connected in common to a source line SL101. Respective source lines SL101 to SL105 in the rows are connected to a common source line SL100.
Furthermore, drains D of the memory cell transistors in the memory cells belonging to a column are connected to a common bit line. For example, the drains D of the memory cell transistors in the memory cells MC11 to MC51 are connected in common to a bit line BL101.
FIG. 49 is a plan view showing a structure of the background-art nonvolatile semiconductor memory device using the configuration of the memory cell array shown in FIG. 48. In FIG. 49, an arrangement of the floating gate, the word line (also used as the control gate), the source line and the isolation insulating film is schematically shown. For example, floating gates 411, 412, and 421 shown in FIG. 49 correspond to the respective floating gates FG in the memory cell transistors of the memory cells MC11, MC12, MC21 shown in FIG. 48.
Further, for example, a source region Sa shown in FIG. 49 corresponds to the respective sources S in the memory cell transistors of the memory cells MC11 and MC21 shown in FIG. 48, and a source region Sd shown in FIG. 49 corresponds to the respective sources S in the memory cell transistors of the memory cells MC31 and MC41 shown in FIG. 48.
Furthermore, for example, a drain region Da shown in FIG. 49 corresponds to the respective drains D in the memory cell transistors of the memory cells MC21 and MC31 shown in FIG. 48, and a drain region Dd shown in FIG. 49 corresponds to the respective drains D in the memory cell transistors of the memory cells MC41 and MC51 shown in FIG. 48.
Referring to FIG. 49, the source lines SL101 and SL102 include the source regions Sa to Sc, the source lines SL103 and SL104 include the source regions Sd to Sf, and the source line SL105 includes the source regions Sg to Si. Each of the source lines SL101 to SL105 is formed by providing a region where no isolation insulating film 112 is formed between the rows.
FIG. 50 is a cross section showing a cross-sectional structure taken along the line X100 of FIG. 49. The source region Sa and the source region Sb are isolated from each other by the full-isolation insulating film 112.
This background-art nonvolatile semiconductor memory device, however, has the following problem. Referring to FIG. 47, this problem will be discussed. As discussed above, in the write operation of data, a high voltage is applied to the drain region 102d and the control gate 106 with a ground potential applied to the source region 102s. At this time, a large number of pairs of electrons and positive holes are generated near the channel region and the drain region 102d through an collision ionization.
In the background-art nonvolatile semiconductor memory device using the SOI substrate, since the body region is in an electrically floating state, the positive holes are accumulated in the body region. Therefore, as the body potential rises, a parasitic bipolar transistor consisting of the source region 102s, the drain region 102d and the body region is driven and as a result, a parasitic bipolar current is carried from the source region 102s towards the drain region 102d, to cause a malfunction. Thus, in the background-art nonvolatile semiconductor memory device, the positive holes are accumulated in the body region due to the electrically floating state of the body region, to drive the parasitic bipolar transistor, thereby disadvantageously causing a malfunction.
The present invention is directed to a nonvolatile semiconductor memory device. According to a first aspect of the present invention, the nonvolatile semiconductor memory device comprises: an SOI substrate in which a semiconductor substrate, an insulating layer and a semiconductor layer are layered in this order; a plurality of memory cell transistors arranged in a matrix, each having a source region and a drain region which are formed away from each other in a main surface of the semiconductor layer, a first gate electrode formed on a body region between the source region and the drain region with an insulating film interposed therebetween, and a second gate electrode formed on the first gate electrode with an insulating film interposed therebetween; an isolation insulating film formed between adjacent ones of the plurality of memory cell transistors in a row direction perpendicular to a direction in which the source region and the drain region of each of the plurality of memory cell transistors are aligned in the main surface of the semiconductor layer, having a bottom surface which does not reach the insulating layer; and an impurity introduction region formed between the source regions included in adjacent ones of the plurality of memory cell transistors in the row direction in the semiconductor layer, having the same conductivity type as the source region has.
According to a second aspect of the present invention, in the nonvolatile semiconductor memory device of the first aspect, the source region or a depletion layer in a pn junction between the source region and the semiconductor layer does not reach the insulating layer.
According to a third aspect of the present invention, in the nonvolatile semiconductor memory device of the second aspect, the drain region or a depletion layer in a pn junction between the drain region and the semiconductor layer does not reach the insulating layer.
According to a fourth aspect of the present invention, in the nonvolatile semiconductor memory device of the second aspect, the drain region or a depletion layer in a pn junction between the drain region and the semiconductor layer reaches the insulating layer.
According to a fifth aspect of the present invention, in the nonvolatile semiconductor memory device of the first aspect, both the source region and the drain region or both depletion layers in pn junctions between the source region and the semiconductor layer and between the drain region and the semiconductor layer reach the insulating layer, and the nonvolatile semiconductor memory device of the fifth aspect further comprises: a word line connected in common to the second gate electrodes included in the plurality of memory cell transistors belonging to a row; a body line connecting the body regions included in the plurality of memory cell transistors belonging to a row; a first driving circuit connected to the word line, for supplying the word line with a first driving signal; and a second driving circuit connected to the body line, for supplying the body line with a second driving signal.
According to a sixth aspect of the present invention, in the nonvolatile semiconductor memory device of the fifth aspect, the first and second driving circuits are arranged on the opposite sides with a memory cell array portion sandwiched therebetween, in which a plurality of memory cells including the plurality of memory cell transistors are arranged.
According to a seventh aspect of the present invention, the nonvolatile semiconductor memory device comprises: an SOI substrate in which a semiconductor substrate, an insulating layer and a semiconductor layer are layered in this order; a plurality of memory cell transistors arranged in a matrix, each having a source region and a drain region which are formed away from each other in a main surface of the semiconductor layer, a first gate electrode formed on a body region between the source region and the drain region with an insulating film interposed therebetween, and a second gate electrode formed on the first gate electrode with an insulating film interposed therebetween; and an isolation insulating film formed between adjacent ones of the plurality of memory cell transistors in a row direction perpendicular to a direction in which the source region and the drain region of each of the plurality of memory cell transistors are aligned in the main surface of the semiconductor layer, having a bottom surface which does not reach the insulating layer, and in the nonvolatile semiconductor memory device of the seventh aspect, the source region or a depletion layer in a pn junction between the source region and the semiconductor layer does not reach the insulating layer, and the drain region or a depletion layer in a pn junction between the drain region and the semiconductor layer reaches the insulating layer.
According to an eighth aspect of the present invention, the nonvolatile semiconductor memory device comprises: an SOI substrate in which a semiconductor substrate, an insulating layer and a semiconductor layer are layered in this order; a plurality of memory cell transistors arranged in a matrix, each having a source region and a drain region which are formed away from each other in a main surface of the semiconductor layer, a first gate electrode formed on a body region between the source region and the drain region with an insulating film interposed therebetween, and a second gate electrode formed on the first gate electrode with an insulating film interposed therebetween; an isolation insulating film formed between adjacent ones of the plurality of memory cell transistors in a row direction perpendicular to a direction in which the source region and the drain region of each of the plurality of memory cell transistors are aligned in the main surface of the semiconductor layer, having a bottom surface which does not reach the insulating layer; a word line connected in common to the second gate electrodes included in the plurality of memory cell transistors belonging to a row; a body line connecting the body regions included in the plurality of memory cell transistors belonging to a row; a first driving circuit connected to the word line, for supplying the word line with a first driving signal; and a second driving circuit connected to the body line, for supplying the body line with a second driving signal, and in the nonvolatile semiconductor memory device of the eighth aspect, both the source region and the drain region or both depletion layers in pn junctions between the source region and the semiconductor layer and between the drain region and the semiconductor layer reach the insulating layer.
According to a ninth aspect of the present invention, in the nonvolatile semiconductor memory device of the eighth aspect, the first and second driving circuits are arranged on the opposite sides with a memory cell array portion sandwiched therebetween, in which a plurality of memory cells including the plurality of memory cell transistors are arranged.
According to a tenth aspect of the present invention, in the nonvolatile semiconductor memory device of any one of the fifth, sixth, eighth and ninth aspects, the second driving circuit supplies the body line which is selected in reading data with a first potential as the second driving signal and supplies the body line which is not selected with a ground potential or a second potential having a polarity reverse to that of the first potential as the second driving signal.
According to an eleventh aspect of the present invention, in the nonvolatile semiconductor memory device of any one of the fifth, sixth, eighth, ninth and tenth aspects, the second driving circuit supplies the body line with the second driving signal before the first driving circuit supplies the word line with the first driving signal.
According to a twelfth aspect of the present invention, in the nonvolatile semiconductor memory device of any one of the seventh to eleventh aspects further comprises: an impurity introduction region formed between the source regions included in adjacent ones of the plurality of memory cell transistors in the row direction in the semiconductor layer, having the same conductivity type as the source region has.
The present invention is also directed to a semiconductor integrated circuit. According to a thirteenth aspect of the present invention, the semiconductor integrated circuit comprises: an SOI substrate in which a semiconductor substrate, an insulating layer and a semiconductor layer are layered in this order; a plurality of memory cell transistors formed in a memory cell array portion of the SOI substrate; and a plurality of low-voltage transistors formed in a low-voltage portion of the SOI substrate, being driven by a voltage lower than a driving voltage of the plurality of memory cell transistors, and in the semiconductor integrated circuit of the thirteenth aspect, the plurality of memory cell transistors and the plurality of low-voltage transistors each have a source region and a drain region which are formed away from each other in the semiconductor layer, the source region or a depletion layer in a pn junction between the source region and the semiconductor layer in each of the plurality of memory cell transistors does not reach the insulating layer, and both the source region and the drain region or both depletion layers in pn junctions between the source region and the semiconductor layer and between the drain region and the semiconductor layer in each of the plurality of low-voltage transistors reach the insulating layer.
According to a fourteenth aspect of the present invention, in the semiconductor integrated circuit of the thirteenth aspect, the depth from a main surface of the semiconductor layer to bottom surfaces of the source region and the drain region of each of the plurality of low-voltage transistors is deeper than that from the main surface of the semiconductor layer to a bottom surface of the source region of each of the plurality of memory cell transistors.
According to a fifteenth aspect of the present invention, in the semiconductor integrated circuit of the thirteenth aspect, the film thickness of the semiconductor layer in the low-voltage portion is thinner than that of the semiconductor layer in the memory cell array portion.
According to a sixteenth aspect of the present invention, the semiconductor integrated circuit of any one of the thirteenth to fifteenth aspects further comprises an isolation insulating film formed in an interface between the memory cell array portion and the low-voltage portion in the semiconductor layer, of which bottom surface reaches the insulating layer.
According to a seventeenth aspect of the present invention, the semiconductor integrated circuit comprises: a substrate having a memory cell array portion in which a plurality of memory cell transistors are formed; a low-voltage portion in which a plurality of low-voltage transistors which are driven by a voltage lower than a driving voltage of the plurality of memory cell transistors are formed; and a high-voltage portion in which a plurality of high-voltage transistors which are driven by a voltage higher than a driving voltage of the plurality of low-voltage portions are formed, and in the semiconductor integrated circuit of the seventeenth aspect, the high-voltage portion and the low-voltage portion are arranged with the memory cell array portion sandwiched.
According to an eighteenth aspect of the present invention, in the semiconductor integrated circuit of the seventeenth aspect, the low-voltage portion is divided into a plurality of circuit blocks, and a radio frequency circuit portion in which a radio frequency circuit is formed is provided in one of the plurality of circuit blocks which is positioned farthest away from the high-voltage portion.
According to a nineteenth aspect of the present invention, in the semiconductor integrated circuit of the eighteenth aspect, the substrate is an SOI substrate in which a semiconductor substrate, an insulating layer and a semiconductor layer are layered in this order, and the semiconductor integrated circuit of the nineteenth aspect further comprises: a first isolation insulating film formed in each of interfaces between the memory cell array portion and the low-voltage portion and between the memory cell array portion and the high-voltage portion in the semiconductor layer, having a bottom surface which reaches the insulating layer; and a second isolation insulating film formed in each of interfaces between the radio frequency circuit portion and other portions in the semiconductor layer, having a bottom surface which reaches the insulating layer and being wider than the first isolation insulating film.
According to a twentieth aspect of the present invention, in the semiconductor integrated circuit of the seventeenth aspect, the substrate is an SOI substrate in which a semiconductor substrate, an insulating layer and a semiconductor layer are layered in this order, and the semiconductor integrated circuit of the twentieth aspect further comprises: a first isolation insulating film formed between adjacent ones of the plurality of memory cell transistors in a main surface of the semiconductor layer, having a bottom surface which does not reach the insulating layer; and a second isolation insulating film formed between adjacent ones of the plurality of low-voltage transistors in the main surface of the semiconductor layer, having a bottom surface which does not reach the insulating layer, and in the semiconductor integrated circuit of the twentieth aspect, the depth from the main surface of the semiconductor layer to the bottom surface of the first isolation insulating film is deeper than that from the main surface of the semiconductor layer to the bottom surface of the second isolation insulating film.
According to a twenty-first aspect of the present invention, in the semiconductor integrated circuit of the seventeenth aspect, the substrate is an SOI substrate in which a semiconductor substrate, an insulating layer and a semiconductor layer are layered in this order, and the semiconductor integrated circuit of the twenty-first aspect further comprises: a first isolation insulating film formed between adjacent ones of the plurality of memory cell transistors in a main surface of the semiconductor layer, in which a first channel cut layer is formed adjacently to a bottom surface thereof; and a second isolation insulating film formed between adjacent ones of the plurality of low-voltage transistors in a main surface of the semiconductor layer, in which a second channel cut layer is formed adjacently to a bottom surface thereof, and in the semiconductor integrated circuit of the twenty-first aspect, the impurity concentration of the first channel cut layer is higher than that of the second channel cut layer.
According to a twenty-second aspect of the present invention, in the semiconductor integrated circuit of the seventeenth aspect, the threshold voltage of each of the plurality of memory cell transistors is higher than that of each of the plurality of low-voltage transistors.
According to a twenty-third aspect of the present invention, the semiconductor integrated circuit comprises: an SOI substrate in which a semiconductor substrate, and insulating layer and a semiconductor layer are layered in this order, having a memory cell array portion in which a plurality of memory cell transistors are formed, a low-voltage portion in which a plurality of low-voltage transistors which are driven by a voltage lower than a driving voltage of the plurality of memory cell transistors are formed, and a high-voltage portion in which a plurality of high-voltage transistors which are driven by a voltage higher than a driving voltage of the plurality of low-voltage portions are formed; and a first isolation insulating film formed in each of interfaces between the memory cell array portion and the low-voltage portion and between the memory cell array portion and the high-voltage portion in the semiconductor layer, having a bottom surface which reaches the insulating layer.
According to a twenty-fourth aspect of the present invention, in the semiconductor integrated circuit of the twenty-third aspect, the high-voltage portion has a portion adjacent to the low-voltage portion, and the semiconductor integrated circuit of the twenty-fourth aspect further comprises: a second isolation insulating film formed in the semiconductor layer in the portion, having a bottom surface which reaches the insulating layer and being wider than the first isolation insulating film.
In the nonvolatile semiconductor memory device of the first aspect of the present invention, the adjacent source regions in the row direction can be electrically connected to each other through the semiconductor layer, thereby consisting a source line.
Further, since the impurity introduction region which has the same conductivity type as the source regions has between the adjacent source regions in the row direction, it is also possible to reduce the resistance of the source line.
In the nonvolatile semiconductor memory device of the second aspect of the present invention, it is possible to avoid the rise of body resistance in the column direction.
Further, also between the adjacent memory cells in the column direction, it is possible to fix the body potential through the semiconductor layer of a portion between the source region and the insulating layer.
In the nonvolatile semiconductor memory device of the third aspect of the present invention, since the body potential can be fixed through the semiconductor layer of a portion between the drain region and the insulating layer in the adjacent memory cell transistors in the column direction, it is possible to improve the capability of fixing the body potential.
In the nonvolatile semiconductor memory device of the fourth aspect of the present invention, since the pn junction capacitance in the pn junction between the drain region and the semiconductor layer, it is possible to maintain the read and write operations of data at high speed and low power consumption.
In the nonvolatile semiconductor memory device of the fifth aspect of the present invention, since a bipolar current can be also carried from the source region to the drain region of the memory cell transistor by driving the body line as well as the word line in performing the write operation of data, it is possible to improve the efficiency in writing data.
In the nonvolatile semiconductor memory device of the sixth aspect of the present invention, since the first driving circuit and the second driving circuit are arranged on the opposite sides with the memory cell array portion sandwiched therebetween, the effect of voltage drop caused by the resistances of the word line and the body line can be offset. This can make the writing characteristics uniform in a plurality of memory cells belonging to a row.
In the nonvolatile semiconductor memory device of the seventh aspect of the present invention, it is possible to avoid the rise of the body resistance in the column direction.
Further, the body potential can be fixed through the semiconductor layer of a portion between the source region and the insulating layer in the adjacent memory cells in the column direction.
Furthermore, since the pn junction capacitance in the pn junction between the drain region and the semiconductor layer can be reduced, it is possible to maintain the read and write operations of data at high speed and low power consumption.
In the nonvolatile semiconductor memory device of the eighth aspect of the present invention, since a bipolar current can be also carried from the source region to the drain region of the memory cell transistor by driving the body line as well as the word line in performing the write operation of data, it is possible to improve the efficiency in writing data.
In the nonvolatile semiconductor memory device of the ninth aspect of the present invention, since the first driving circuit and the second driving circuit are arranged on the opposite sides with the memory cell array portion sandwiched therebetween, the effect of voltage drop caused by the resistances of the word line and the body line can be offset. This can make the writing characteristics uniform in a plurality of memory cells belonging to a row.
In the nonvolatile semiconductor memory device of the tenth aspect of the present invention, it is possible to avoid a disturb failure.
In the nonvolatile semiconductor memory device of the eleventh aspect of the present invention, even if the resistance of the body line is higher than that of the word line, it is possible to avoid the lag of the second driving signal behind the first driving signal.
In the nonvolatile semiconductor memory device of the twelfth aspect of the present invention, the resistance of the source line can be reduced by forming the impurity introduction region between the adjacent source regions in the row direction.
In the semiconductor integrated circuit of the thirteenth aspect of the present invention, it is possible to improve the capability of fixing the body potential in the memory cell array portion while avoiding a decrease in operation speed and an increase in power consumption which are caused as the pn junction capacitance increases in the low-voltage portion.
In the semiconductor integrated circuit of the fourteenth aspect of the present invention, both the source region and the drain region or both the depletion layers in the pn junctions between the source region and the semiconductor layer and between the drain region and the semiconductor layer can reach the insulating layer only in the low-voltage portion.
In the semiconductor integrated circuit of the fifteenth aspect of the present invention, both the source region and the drain region or both the depletion layers in the pn junctions between the source region and the semiconductor layer and between the drain region and the semiconductor layer can reach the insulating layer only in the low-voltage portion.
Further, the source region in the memory cell array portion which does not reaches the insulating layer and the source region and the drain region in the low-voltage portion which reach the insulating layer can be formed through the same ion implantation process.
In the semiconductor integrated circuit of the sixteenth aspect of the present invention, it is possible to prevent the noises generated in the memory cell array portion and the low-voltage portion from being mutually propagated through the semiconductor layer. Therefore, the semiconductor integrated circuit of the sixteenth aspect is unlikely to be affected by the noises.
In the semiconductor integrated circuit of the seventeenth aspect of the present invention, since the high-voltage portion and the low-voltage portion are arranged on the opposite sides of the substrate with said memory cell array portion sandwiched therebetween, it is possible to prevent the low-voltage portion from being affected by the noise generated in the high-voltage portion which is likely to become a source of noise.
In the semiconductor integrated circuit of the eighteenth aspect of the present invention, it is possible to relieve the effect of noise generated in the high-voltage portion on the radio frequency circuit which is likely to be affected by the noise.
In the semiconductor integrated circuit of the nineteenth aspect of the present invention, by forming the first isolation insulating film, it is possible to prevent the noises generated in the memory cell array portion, the low-voltage portion and the high-voltage portion from being mutually propagated through the semiconductor layer. Therefore, the semiconductor integrated circuit of the nineteenth aspect is unlikely to be affected by the noises.
Further, by forming the second isolation insulating film, it is possible to reduce the effect of the noise generated in regions other than the radio frequency circuit portion on the radio frequency circuit portion.
In the semiconductor integrated circuit of the twentieth aspect of the present invention, it is possible to enhance the isolation breakdown voltage of the first isolation insulating film in the memory cell array portion where a voltage higher than that in the low-voltage portion is dealt.
In the semiconductor integrated circuit of the twenty-first aspect of the present invention, it is possible to enhance the isolation breakdown voltage of the first isolation insulating film in the memory cell array portion where a voltage higher than that in the low-voltage portion is dealt.
In the semiconductor integrated circuit of the twenty-second aspect of the present invention, it is possible to enhance a punch through resistance of a transistor in the memory cell array portion.
In the semiconductor integrated circuit of the twenty-third aspect of the present invention, it is possible to prevent the noises generated in the memory cell array portion, the low-voltage portion and the high-voltage portion from being mutually propagated through the semiconductor layer. Therefore, the semiconductor integrated circuit of the twenty-third aspect is unlikely to be affected by the noises.
In the semiconductor integrated circuit of the twenty-fourth aspect of the present invention, by forming the second isolation insulating film having a high isolation breakdown voltage, it is possible to prevent the mutual effect of noises generated in the adjacent high-voltage portion and the low-voltage portion.
An object of the present invention is to provide a nonvolatile semiconductor memory device which avoids accumulation of the positive holes in the body region and therefore causes no malfunction due to driving of the parasitic bipolar transistor.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.